Turning to FIG. 1, a conventional level shifter 100 can be seen. Level shifter 100 is generally comprised of drivers 102 and 104 (which operate in different voltage domains) with capacitors C1 and C2 (which should be sufficiently large so as to have a sufficiently low cut-off frequency) coupled therebetween. For higher voltage applications, capacitors C1 and C2 can be replaced with capacitor strings. Typically, each of drivers 102 and 104 has a pair of signal or data paths (which are generally comprised of inverters 106-1 to 106-4 and 108-1 to 108-4) so as to be able to generate differential signal DOUT/ DOUT from differential signal DIN/ DIN. Latch 110 (which is coupled between the signals paths of driver 104 and which are generally comprised of inverters 108-5 and 108-6) is also included to drive the signal to rail.
A problem with this arrangement, however, is that, as switching occurs, capacitors C1 and C2 are repeatedly charged and discharged. As a result, the voltage on the capacitors C1 and C2 varies, distorting the signal DIN/ DIN as it traverses the level shifter 100 (as shown in FIG. 2). Additionally, jitter is introduced, which distorts the eye-opening pattern (as shown in FIG. 3). Thus, there is a need to compensate for distortion in level shifters.
Some other examples of conventional systems are: U.S. Patent Pre-Grant Publ. No. 2006/0091907; Rajapandian et al., “High-voltage power delivery through charge recycling,” IEEE J. of Solid-State Circuits, Vol. 41, No. 6, pp. 1400-1410, June 2006; and Breussegem et al., “Monolithic capactivie DC-DC Converter with Single Boundary-Multiphase Control and Voltage Domain Stacking in 90 nm CMOS,” IEEE J. of Solid-State Circuits, Vol. 46, No. 7, pp. 1715-1727, July 2011.